IEEE Std 1149.10-2017 pdf download – IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture.
control character: Any of the special symbols used in serial communication encodings. 8B/10B, for instance, defines twelve control symbols. All of the control characters in this standard are shown and defined as unencoded hexadecimal values of eight bits in width. CRC32: Cyclical Redundancy Check. All references to CRC32 in this document refer to the 32-bit computation as documented in IEEE Std 802.3. 4 Enable_1149_10: A signal that is an input to the PEDDA when at least one scan-channel is shared with an IEEE 1149.1 TAP. When it is asserted, the PEDDA provides access to one or more scan-channels from a HSTAP. When it is de-asserted, the PEDDA provides access to one or more scan-channels from the IEEE 1149.1 TAP. An IEEE 1149.1 PDL iProc with the same name documents one method to assert the signal, other methods are left to the designer. high-speed test access port (HSTAP): The HSTAP is the input/output pins and circuitry that deliver data to a PEDDA. It is the test access port of this standard and is not a high-speed version of the IEEE 1149.1 TAP. The HSTAP may include common serial encoding/decoding methods such as 8B/10B, 128B/130B, or others. IEEE 1149.10 interface: A high-speed test access port (HSTAP) and packet encoder/decoder and distribution architecture (PEDDA). instruction register: Refers to the IEEE 1149.1 instruction register. Bit “I” of the ICSU defined section in the scan packet indicates if there is an operation from a HSTAP and PEDDA to an IEEE 1149.1 instruction register. All other “instruction” registers, such as the IEEE 1500 wrapper instruction register, are treated as IEEE 1149.1 test data registers. lane: A serial data transmission path with one transmit and receive pair. The terminology commonly is used with differential signaling, however, for this standard, a single-ended transmit and receive pair also make up a lane.