IEEE Std 1804-2017 pdf download – IEEE Standard for Fault Accounting and Coverage Reporting (FACR) for Digital Modules.
fault detection: The condition when the presence of a stuck-at fault in the circuit causes the logic value measured at an observation point in the circuit to differ from the logic value expected in the fault-free circuit. For example, a fault is detected when a 0 is expected but a 1 was observed (denoted 0/1), as well as 1/0. A fault is possibly detected in the 0/X and 1/X cases. fault detection status: The classification given to a fault in the fault universe based on its fault detection results during test generation or fault simulation. Fault status can be categorized as detected, possibly detected, undetected, ATPG untestable or structurally untestable, with different classes in each. (Refer to Table 1) Syn: fault status. fault equivalence: Two stuck-at faults are equivalent if they have exactly the same test set, i.e., every test which detects one fault also detects the other fault. fault grading: A procedure that rates testability by relating the number of faults that can in fact be detected with a test vector set under consideration to the total number of conceivable faults. fault list: A list of faults for a circuit, one per line, containing three fields (in some defined order with some defined delimiters): the name of the fault-site, the polarity of the fault, and the detection status of the fault. The two examples included in this standard are: — Fault-site (with full hierarchy) <comma or spaces> Fault Polarity (0 or 1) <comma or spaces> Fault Status (Fault Category as enumerated in Table 1) — Fault Polarity (0 or 1) <comma or spaces> Fault Status (Fault Category as enumerated in Table 1) <comma or spaces> Fault-site (with full hierarchy)
These are faults on nets for which the good circuit simulation results in a known value on the net (0 or 1), or a known high-impedance condition on a net (denoted by Z), whereas the faulty circuit simulation results in an unknown value (X), due to the fault resulting in some non-initialization (e.g., on a reset line, denoted by X), or a delayed response (e.g., due to faulty or weak pull-up, pull-down controls, denoted by X), or a high- impedance state (e.g., on the enable control of a tristate buffer, denoted by Z). Analysis would show that the fault is not definitely detected, but only possibly detected due to non-determinism introduced by the Z or X value. In a circuit implemented in silicon, however, a Z or X value on a specific net may resolve into a 0 or 1 value. If the faulty net value is 1 (0) and the fault-free value is 0 (1), the fault is detected. If the value on the net in the absence or presence of the fault is the same, the fault is not detected. If the specific value on the net cannot be evaluated (because it is either Z or X), such faults are classified as possibly detected. The weighted number of faults reported as possibly detected is denoted as: (count of possibly detected faults) × (possible credit) Where possible credit is a weight specified by the user (with value ranging between 0 and 1) denoting the certainty of this detection. Possibly detected faults are also included in the overall count of detected faults.