IEEE Std 2416-2019 pdf download – IEEE Standard for Power Modeling to Enable System Level Analysis.
1.1 Scope This standard describes a parameterized and abstracted power model enabling system, software, and hardware intellectual property (IP)–centric power analysis and optimization. It defines concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature (PVT) independence; power and thermal management interface; and workload and architecture parameterization. Such models are suitable for use in software development flows and hardware design flows, as well as for representing both pre–silicon-estimated and post–silicon-measured data. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models to help guide development and usage of other related power, workload, and functional modeling standards, such as UPF IEEE Std 1801™-2015, SystemC IEEE Std 1666™-2011, and SystemVerilog IEEE Std 1800™-2012. Beyond defining the concepts and related standard requirements, this standard also recommends the use of other relevant design flow standards (e.g., IP-XACT IEEE Std 1685™-2014 [B2] 2 ), with the objective of enabling more complete and usable power-aware design flows. 1.2 Purpose This standard supports the ability to develop accurate, efficient, and interoperable power models for complex designs, to be used with a variety of commercial products throughout an electronic system design, analysis, and verification flows.
1.3 Key aspects and considerations This standard describes a PVT-independent modeling capability that can serve up power data throughout the entire System-on-Chip (SoC) development flow from IEEE 1801 system-level power estimation all the way down to gate-level power calculation. Contributor-based modeling techniques are employed to achieve PVT independence, and multilevel modeling concepts enable a single model to serve various abstraction levels. Contributors are separable, summable components of power consumption that depend on parameters such as transistor widths and stacks, as well as on charging capacitances. Contributors offer the capability to do a “late binding” of specific PVT conditions to an IP model, avoiding the need to characterize the target IP up front under particular PVT conditions. This standard addresses three separate, but related, modeling concerns: 1) interfaces to other modeling standards, such as IEEE Std 1801-2015, as well as to existing electronic design automation (EDA) tools; 2) persistent data representation and storage; and 3) model evaluation — the conversion of contributor data into energy and power data.